Conventional dynamic logic provides excellent opportunities for significant performance improvement. Such dynamic logic often entails a number of special requirements which often can be met only at the expense of additional circuit complexity. This circuit complexity occasionally includes the expense of burdensome duplication of circuitry not ordinarily needed in logically equivalent static logic designs. For example, domino logic is the conventional form of dynamic logic being used in current dynamic logic designs. In domino logic, the implementation of non-unate logic, such as XOR logic, requires dual-rail signals. Such dual-rail signals clearly entail the generation of the often otherwise unavailable phase of the signal or signals. Because XOR gates are a reasonably common occurrence, the generation of dual-rail versions of signals is a frequent requirement and this is a more complex circuit function than the simple inversion used in static logic.
Other restrictions and drawbacks are encountered when a hold-time latch is required. Hold-time is defined as the amount of time for which a data signal must remain valid after the active clock edge has occurred or after the active clock time interval has begun for the case of dynamic logic, in order to obtain a valid logical result. In contrast to the register-based logic of static designs, domino logic uses a latch-based approach. A hold-time latch is commonly integrated into the consuming or receiving gate for best performance and circuit economy. This gives rise to special circuit considerations which must be considered to make the circuit function implementation successful.